Asynchronous, or clockless, logic–an alternative to standard digital circuits that avoids many of their problems–is beginning to look attractive for embedded designs in consumer electronics and mobile ...

At 0.18 micron and below, handling crosstalk becomes a significant design challenge. Historically safe and pervasive design techniques may now increase crosstalk, and must be reviewed for suitability.

Part of the Planning Process in DO-254 is knowing the appropriate FPGA tools and capabilities that you need and intend to use for your FPGA design. Particularly if your FPGA device operates with ...

There are a number of interesting technologies to keep an eye on in term of how and when they could be adopted for use in SoC design today, some of which include gallium arsenide, GPGPUs, 3D ICs and ...

You only need to validate one core of a CMP design. So if that core is simpler, validation is easier. And you have to worry about the rest of the logic no matter what your core design is. You dont get ...

In the simulation and verification world, particularly with regard to system-on-a-chip (SoC) design closure, certain fault types have made their way to silicon with greater frequency. Many of today's ...

One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.

Pity the poor TTL computer aficionado. It’s an obsession, really — using discrete logic chips to scratch-build a computer that would probably compare unfavorably to an 80s era 8-bit machine in terms ...

Proceedings of the National Academy of Sciences of the United States of America, Vol. 97, No. 8 (Apr. 11, 2000), pp. 4339-4344 (6 pages) Most clock genes encode transcription factors that interact to ...