EDN

Building an FPGA FIFO without using logic resources

Today, FPGA designers are using these flexible devices to perform everything from simple glue logic tasks to implementing complicated system on a chip (SoC) functions. The efficiency and ease of ...
EDN

Tutorial: Designing an FPGA from scratch – It’s like déjà vu all over again!

Where does the time go? About four years ago as I pen these words, I was introduced to expert Swedish ASIC designer Sven-Åke Andersson. At that time, Sven was aware that, with their increasing NRE ...
Business Wire

DVCon Europe “Must See”: Aldec Tutorial and Demonstration on Adopting Easier UVM to Enable FPGA-Based Acceleration

MUNICH--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, is supporting the second Annual DVCon Europe ...
Electronic Design

1.5-GHz FPGA Takes Clock Gating To The Max

Flexibility is key to FPGA success, but speed is equally important. Achronix almost triples the throughput of the system by taking clock gating to the extreme. The Achronix Speedster FPGAs use a ...