Hillsboro, Ore.—Lattice Semiconductor Corp. has released the LatticeECP2M FPGA family, consisting of low cost devices that offer high-speed embedded SerDes I/O plus a pre-engineered Physical Coding ...
Two core products, the 10 Gigabit Physical Coding Sublayer (PCS) and the Media Access Controller (MAC), are intended for use in Xilinx’s Virtex-II and Virtex-II Pro field programmable gate arrays ...
Physical Coding Sublayer (PCS) add-on to the successful MAC-1G controller provides new opportunities for an already wide range of possible implementations. Gliwice & Bielsko-Biala, Poland, June ...
SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled the Cadence ® High-Speed Ethernet Controller IP family, which enables complete Ethernet subsystem ...
Ethernet has become the primary network protocol of choice for the required server-to-server communication in hyperscale data centers, as it allows hyperscalers to ...
SANTA CLARA, Calif.--(BUSINESS WIRE)--The 25 Gigabit Ethernet Consortium, originally established to develop 25, 50 and 100 Gbps Ethernet specifications, announced today it has changed its name to the ...
Aldec released the latest version of its Riviera-PRO verification platform, adding QEMU Bridge to enable hardware/software co-simulation of designs intended to run on SoC FPGAs. Other features include ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results
Feedback