EDN

SmartDV Adds Support for Verilator Open Source HDL Verilog Simulator

SmartDV™ Technologies announced support for Verilator, the free, open-source hardware description language (HDL) simulator, becoming the first Verification Intellectual Property (VIP) provider to do ...
Design-Reuse

SmartDV's TileLink, Verilator VIP on Full Display at RISC-V Summit

WHAT: Will highlight new additions to its extensive and broad portfolio of VIP that support TileLink, the chip-scale interconnect standard, and the Verilator open-source hardware description language ...
Hackaday

fpga emulation

Ever want to play with an FPGA, but don’t have the hardware? Now, if you have one of those ever-abundant Pi Picos, you can start playing with Verilog without getting an FPGA board. The FakePGA project ...
Hackaday

system verilog

Hundreds of variations of open-source CPUs written in an HDL seem to float around the internet these days (and that’s a great thing). Many are RISC-V, an open-source instruction set (ISA), and are ...
Ars Technica

Open Source VHDL (or similar) CPU Simulation Software

Hey all, my last semester of college we had to develop the microarchitecture for a RISC processor. My group was ultimately unsuccessful (our L2 cache had some serious issues), but I wouldn't mind ...
Design-Reuse

SmartDV Adds Support for Verilator Open Source HDL Verilog Simulator

SAN JOSE, CALIF. –– October 1, 2019 –– SmartDV™ Technologies today announced support for Verilator, the free, open-source hardware description language (HDL) simulator, becoming the first Verification ...